The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to noise reduction during simultaneous operation of a flash memory device.
Flash memory devices are known which store data in non-volatile memory cells. The data may be subsequently read from individually addressed storage locations. Memory cells can be programmed by applying suitable programming voltages. Similarly, memory cells can be erased to a preprogrammed state by applying suitable erase voltages.
To enhance user convenience, a new family of flash memory devices has been developed providing simultaneous operation. These devices are separated into two banks of memory cells. Each bank is further divided into a number of sectors of a predetermined size. A write operation may be initiated in one bank while simultaneously reading from the other bank. Writing encompasses the erase and verify procedures and is typically done on a sector-by-sector basis. Because the erase and verify operations are slow relative to read access, and because erasing is typically done on sectors of data, many read operations can occur while a write operation is underway.
It has been observed that a large amount of noise is introduced into the memory device during the erase and verify operations. The noise is particularly severe when crossing sector boundaries, that is, when changing the address from one sector to another. This noise can affect the read operation which is occurring simultaneously. The noise can reduce the sensing margin in the sense amplifiers which detect the states of individually addressed memory cells. This can corrupt the data being sensed or increase the time required for accurate sensing of memory cell data states. Both of these conditions are to be avoided.
In one prior device permitting simultaneous operation, read operations are monitored during a write operation in one bank. If a read signal is detected when the embedded write operation is attempting to change multiple address signals as part of an erase or verify operation, the embedded operation will wait for the read operation to occur. While the idea behind this prior implementation is acceptable, its implementation has not been acceptable in commercial devices.
Accordingly, there is a need for an improved method and apparatus for reducing noise during simultaneous operation of a memory such as a flash memory device.